Data-Flow Analysis in the Memory Management

of Real-Time Multimedia Processing Systems

In real-time multimedia processing systems a very large part of the power consumption is due to the data storage and data transfer. A typical system architecture includes custom hardware (application-specific accelerator datapaths and logic), programmable hardware (DSP core and controller), and a distributed memory organization which is usually expensive in terms of power and area cost. Data transfer and memory access operations typically consume more power than a datapath operation. Moreover, the area cost is often largely dominated by memories. Hence, the optimization of the memory architecture is a crucial step in the design methodology for this type of applications.

In deriving an optimized memory architecture, memory size estimation/computation is an important step in the data transfer and storage exploration stage. Part of this project investigates non-scalar methods for computing exactly the memory size in real-time multimedia algorithms. This approach uses novel algebraic techniques specific to the data-flow analysis used in modern compilers. In contrast with previous works which utilized only approximate methods due to the size of the problems (in terms of number of scalars), this research aims to obtain exact determinations even for large applications. In addition, this research will address novel memory computation topics: dealing with (a large class of) parametric specifications, since many multimedia applications often contain parameters (e.g., the dimensions of image frames), and dealing with parallel loops in order to address high-throughput applications where parallelism was extracted from a sequential code in a preprocessing stage.

The research project will address the problem of deriving a multilevel memory architecture optimized for area and/or power, subject to performance constraints, which is considered a top synthesis problem by the Semiconductor Research Corporation. Another research direction will be the ``optimal'' mapping of data from an embedded application code into the on-chip SRAM or the off-chip DRAM for maximizing the overall memory access performance of the application.

This research employs extensively data-flow analysis techniques specific to compilers and code transformations. Data-flow analysis is a steering mechanism which allows more exploration freedom than a scheduling-based investigation, since the memory management tasks usually need only relative lifetime information (rather than exact), and data-flow analysis is able to conveniently provide the necessary data. Moreover, data-flow analysis enables the study of memory management tasks at the desired level of granularity -- between whole array and the scalar level -- trading-off computational effort, solution accuracy and optimality.