Selected List of Publications

Books, chapters in books

B1.

F. Catthoor, S. Wuytack, E. De Greef, F. Balasa, L. Nachtergaele, A. Vandecapelle, ``Custom Memory Management Methodology: Exploration of Memory Organization for Embedded Multimedia System Design,'' Boston: Kluwer Academic Publishers, 1998.

B2.

F. Catthoor, S. Wuytack, E. De Greef, F. Balasa, P. Slock, ``System exploration for custom low power data storage and transfer,'' chapter in ``Digital Signal Processing for Multimedia Systems,'' K. Parhi, T. Nishitani (eds.), New York: Marcel Dekker Inc., 1999.

Journal papers

J1.

F. Franssen, F. Balasa, M. van Swaaij, F. Catthoor, H. De Man, ``Modeling multi-dimensional data and control flow,'' IEEE Trans. on VLSI Systems, Vol. 1, No. 3, pp. 319-327, Sept. 1993. (pdf file)

J2.

F. Balasa, F. Franssen, F. Catthoor, H. De Man, ``Transformation of nested loops with modulo indexing to affine recurrences,'' J. Parallel Processing Letters, Vol. 4, No. 3, pp. 271-280, 1994.

J3.

F. Balasa, F. Catthoor, H. De Man, ``Background memory area estimation for multi-dimensional signal processing systems,'' IEEE Trans. on VLSI Systems, Vol. 3, No. 2, pp. 157-172, June 1995. (pdf file)

J4.

F. Balasa, F. Catthoor, H. De Man, ``Practical solutions for counting scalars and dependences in ATOMIUM -- a memory management system for multi-dimensional signal processing,'' IEEE Trans. on Comp.-Aided Design of IC's and Systems, Vol. 16, No. 2, pp. 133-145, Feb. 1997. (pdf file)

J5.

F. Balasa, K. Lampaert, ``Symmetry within the sequence-pair representation in the context of placement for analog design,'' IEEE Trans. on Comp.-Aided Design of IC's and Systems, Vol. 19, No. 7, pp. 721-731, July 2000. (pdf file)

J6.

F. Balasa, S.C. Maruvada, ``Using non-slicing topological representations for analog placement,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences (Special section on VLSI Design and CAD Algorithms), Japan, Vol. E84-A, No. 11, pp. 2785-2792, Nov. 2001. (pdf file)

J7.

S.C. Maruvada, K. Krishnamoorthy, F. Balasa, L.M. Ionescu, ``Red-black interval trees in device-level analog placement,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences (Special section on VLSI Design and CAD Algorithms), Japan, Vol. E86-A, No. 12, pp. 3127-3135, Dec. 2003. (pdf file)

J8.

F. Balasa, S.C. Maruvada, K. Krishnamoorthy, ``On the exploration of the solution space in analog placement with symmetry constraints,'' IEEE Trans. on Comp.-Aided Design of IC's and Systems, Vol. 23, No. 2, pp. 177-191, Feb. 2004. (pdf file)

J9.

H. Zhu, I.I. Luican, F. Balasa, ``Memory size computation for real-time multimedia applications based on polyhedral decomposition,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences (Special section on VLSI Design and CAD Algorithms), Japan, Vol. E89-A, No. 12, pp. 3378-3386, Dec. 2006. (pdf file)

J10.

F. Balasa, H. Zhu, I.I. Luican, ``Computation of storage requirements for multi-dimensional signal processing applications,'' IEEE Trans. on VLSI Systems, Vol. 15, No. 4, pp. 447-460, April 2007. (pdf file)

J11.

I.I. Luican, H. Zhu, F. Balasa, ``Computation of the minimum data storage and applications in memory management for multimedia signal processing,'' Integrated Computer-Aided Engineering, IOS Press, Vol. 15, No. 2, pp. 181-196, 2008.

J12.

F. Balasa, P.G. Kjeldsberg, A. Vandecappelle, M. Palkovic, Q. Hu, H. Zhu, F. Catthoor, ``Storage estimation and design space exploration methodologies for the memory management of signal processing applications,'' to be published in J. VLSI Signal Processing Systems, Springer, Special Issue on the 20th Anniversary of the IEEE Intn'l Conf. on Application-Specific Systems, Architectures, and Processors, 2008.

Conference papers

C1.

F. Balasa, F. Catthoor, H. De Man, ``Exact evaluation of memory area for multi-dimensional signal processing systems,'' Proc. IEEE/ACM Int. Conf. on Comp.-Aided Design (ICCAD 1993), pp. 669-672, Santa Clara CA, Nov. 1993. (pdf file)

C2.

F. Balasa, F. Catthoor, H. De Man, ``Dataflow-driven memory allocation for multi-dimensional signal processing systems,'' Proc. IEEE/ACM Int. Conf. on Comp.-Aided Design (ICCAD 1994), pp. 31-34, San Jose CA, Nov. 1994. (pdf file)

C3.

L. Nachtergaele, F. Catthoor, F. Balasa, F. Franssen, E. De Greef, H. Samson, H. De Man, ``Optimization of memory organization and partitioning for decreased size and power in video and image processing systems,'' Proc. IEEE Int. Workshop on Memory Technology, Design and Testing, pp. 82-87, San Jose CA, Aug. 1995. (pdf file)

C4.

P. Grun, F. Balasa, N. Dutt, ``Memory size estimation for multimedia applications,'' Proc. of the 6th IEEE/ACM Int. Workshop on Hardware/Software Codesign (CODES 1998), pp. 145-149, Seattle WA, March 1998. (pdf file)

C5.

F. Balasa, K. Lampaert, ``Module placement for analog layout using the sequence-pair representation,'' Proc. of the 36th ACM/IEEE Design Automation Conf. (DAC 1999), pp. 274-279, New Orleans LA, June 1999. (pdf file)

C6.

Y.-X. Pang, F. Balasa, K. Lampaert, C.-K. Cheng, ``Block placement with symmetry constraints based on the O-tree non-slicing representation,'' Proc. of the 37th ACM/IEEE Design Automation Conf. (DAC 2000), pp. 464-467, Los Angeles CA, June 2000. (pdf file)

C7.

F. Balasa, ``Modeling non-slicing floorplans with binary trees,'' Proc. IEEE/ACM Int. Conf. on Comp.-Aided Design (ICCAD 2000), pp. 13-16, San Jose CA, Nov. 2000. (pdf file)

C8.

F. Balasa, ``Device-level placement for analog layout: an opportunity for non-slicing topological representations,'' Proc. Asia and South-Pacific Design Automation Conf. (ASP-DAC 2001), pp. 281-286, Yokohama, Japan, Jan.-Feb. 2001. (pdf file)

C9.

F. Balasa, W. Geurts, F. Catthoor, H. De Man, ``Solving large scale assignment problems in high-level synthesis by approximate quadratic programming,'' Proc. of the 11th ACM Great Lakes Symposium on VLSI, pp. 19-24, West Lafayette IN, March 2001.

C10.

S.C. Maruvada, K. Krishnamoorthy, F. Balasa, ``Block placement using the segment tree data structure from computational geometry,'' Proc. of the 45th IEEE Int. Midwest Symposium on Circuits and Systems, Vol. II, pp. 111-114, Tulsa OK, Aug. 2002. (pdf file)

C11.

F. Balasa, S.C. Maruvada, K. Krishnamoorthy, ``Efficient solution space exploration based on segment trees in analog placement with symmetry constraints,'' Proc. IEEE/ACM Int. Conf. on Comp.-Aided Design (ICCAD 2002), pp. 497-502, San Jose CA, Nov. 2002. (pdf file)

C12.

F. Balasa, S.C. Maruvada, K. Krishnamoorthy, ``Using red-black interval trees in device-level analog placement with symmetry constraints,'' Proc. Asia and South-Pacific Design Automation Conf. (ASP-DAC 2003), pp. 777-782, Kitakyushu, Japan, Jan. 2003. Nominated for the Best Paper Award. (pdf file)

C13.

S.C. Maruvada, K. Krishnamoorthy, S. Annojvala, F. Balasa, ``Placement with symmetry constraints for analog layout using red-black trees,'' Proc. IEEE Int. Symposium on Circuits and Systems (ISCAS 2003), Vol. V, pp. 489-492, Bangkok, Thailand, May 2003. (pdf file)

C14.

K. Krishnamoorthy, S.C. Maruvada, F. Balasa, ``Fast evaluation of symmetric-feasible sequence-pairs for analog topological placement,'' Proc. of the 5th IEEE Int. Conf. on ASIC (ASICON 2003), vol. 1, pp. 71-74, Beijing, P.R. China, Oct. 2003. (pdf file)

C15.

H. Zhu, K. Chandramouli, Y. Yue, F. Balasa, ``Algebraic techniques in the memory size computation of multimedia processing applications,'' Proc. of the 2nd IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMEDIA 2004), pp. 67-72, Stockholm, Sweden, Sept. 2004. (pdf file)

C16.

K. Krishnamoorthy, S.C. Maruvada, F. Balasa, ``Analog topological placement with symmetry constraints using a O(n log log n) evaluation algorithm,'' Proc. of the 12th IEEE Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI 2004), pp. 379-386, Kanazawa, Japan, Oct. 2004. (pdf file)

C17.

S.C. Maruvada, A. Berkman, K. Krishnamoorthy, F. Balasa, ``Deterministic skip lists in analog topological placement,'' Proc. of the 6th IEEE Int. Conf. on ASIC (ASICON 2005), vol. 2, pp. 756-759, Shanghai, P.R. China, Oct. 2005. (pdf file)

C18.

H. Zhu, I.I. Luican, F. Balasa, ``Memory size computation for multimedia processing applications,'' Proc. Asia & South-Pacific Design Automation Conf. (ASP-DAC 2006), pp. 802-807, Yokohama, Japan, Jan. 2006. (pdf file)

C19.

I.I. Luican, H. Zhu, F. Balasa, ``Novel algorithm for the exact computation of storage requirements based on the decomposition of integral polyhedra,'' Proc. of the 13th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI 2006), pp. 15-20, Nagoya, Japan, Apr. 2006.

C20.

F. Balasa, P.G. Kjeldsberg, M. Palkovic, A. Vandecapelle, F. Catthoor, ``Loop transformation methodologies for array-oriented memory management'' (invited paper), Proc. of the 17th IEEE Int. Conf. on Application-Specific Systems, Architectures and Processors (ASAP 2006), pp. 205-212, Steamboat Springs CO, Sept. 2006. (pdf file)

C21.

I.I. Luican, H. Zhu, F. Balasa, ``Formal model of data reuse analysis for hierarchical memory organizations,'' Proc. IEEE/ACM Int. Conf. on Comp.-Aided Design (ICCAD 2006), pp. 595-600, San Jose CA, Nov. 2006. (pdf file)

C22.

I.I. Luican, H. Zhu, F. Balasa, ``Signal-to-memory mapping analysis for multimedia signal processing,'' Proc. Asia & South-Pacific Design Automation Conf. (ASP-DAC 2007), pp. 486-491, Yokohama, Japan, Jan. 2007. (pdf file)

C23.

H. Zhu, I.I. Luican, F. Balasa, ``Mapping multi-dimensional signals into hierarchical memory organizations,'' Proc. ACM/IEEE Design Automation and Test in Europe (DATE 2007), pp. 385-390, Nice, France, April 2007. (pdf file)

C24.

I.I. Luican, H. Zhu, F. Balasa, ``Computation of the minimum data storage for multi-dimensional signal processing,'' Proc. IEEE Int. Conf. on Acoustics, Speech, and Signal Processing (ICASSP 2007), vol. II, pp. 25-28, Honolulu HI, April 2007. Nominated for the Best Student Paper Award.. (pdf file)

C25.

K. Krishnamoorthy, S.C. Maruvada, F. Balasa, ``Topological placement with multiple symmetry groups of devices for analog layout design,'' Proc. IEEE Int. Symposium on Circuits and Systems (ISCAS 2007), pp. 2032-2035, New Orleans LA, May 2007. (pdf file)

C26.

I.I. Luican, H. Zhu, F. Balasa, ``Evaluation of storage requirements and applications in the memory management for multidimensional signal processing systems,'' Proc. IEEE Conf. Electro / Information Technology, pp. 427-432, Chicago IL, May 2007.

C27.

I.I. Luican, H. Zhu, F. Balasa, Dhiraj K. Pradhan, ``Reducing the dynamic energy consumption in the multi-layer memory of embedded multimedia processing systems,'' Proc. of the 14th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI 2007), pp. 42-48, Sapporo, Japan, Oct. 2007. (pdf file)

C28.

I.I. Luican, H. Zhu, F. Balasa, ``Mapping model with inter-array memory sharing for multidimensional signal processing,'' Proc. IEEE/ACM Int. Conf. on Comp.-Aided Design (ICCAD 2007), pp. 160-165, San Jose CA, Nov. 2007. (pdf file)

C29.

I.I. Luican, H. Zhu, F. Balasa, ``Efficient assignment algorithm for mapping multidimensional signals into the physical memory,'' Proc. IEEE Int. Conf. Acoustics, Speech, and Signal Processing (ICASSP 2008), pp. 1409-1412, Las Vegas NV, April 2008. (pdf file)

Patents

P1.

F. Balasa, F. Catthoor, H. De Man, ``Background memory allocation for multi-dimensional signal processing,'' U.S. Patent No. 5742814, issue date: April 21, 1998.

P2.

F. Balasa, K. Lampaert, ``A method for automated placement of cells in an integrated circuit layout,'' U.S. Patent No. 6550046, issue date: April 15, 2003.